Double-gate MOSFETs have better scaling properties than the conventional single-gated MOSFETs. The two gates are preferably defined by a self-aligned process to minimize parasitic capacitance. Examples of such structures are described, for example, in U.S. Pat. No. 5,773,331 to Solomon et al., entitled “Method for making single and double gate field effect transistors with sidewall source-drain contacts” and in U.S. Pat. No. 6,642,115 to Cohen et al., entitled “Double-gate FET with planarized surfaces and self-aligned silicides”.
FIG. 1 illustrates a typical double-gate MOSFET structure comprising a back gate A103, a back-gate dielectric A104, a semiconductor, typically silicon, channel A105, a top-gate dielectric A107, and a top-gate A108. Silicides A109 and A114 are formed over the top-gate A108 and the source and drain regions A115. The useful portion of the back-gate A103 is that segment which overlaps the channel region A105. The length of this segment is labeled in FIG. 1 as Lbg. The capacitance between the back-gate A103 and the channel A105 in that segment is Cbg. This is a useful capacitance since it allows the back-gate to control the charge in the channel. The back-gate A103 extends laterally by two segments of length Lext—s and Lext—d. The length Lext—s (and similarly Lext—d) is mainly determined by the size of the source/drain regions A115 lateral extension with a small addition that equals to the spacer A111 footprint. The capacitance between the back-gate A103 and the source and drain regions A115 is Cext—s and Cext—d respectively. This capacitance, also known as back-gate to source/drain overlap capacitance, is a parasitic capacitance and needs to be minimized in order to increase the overall speed of the semiconductor device.
To reduce the overlap capacitance to the back-gate, the lateral dimension of the source and drain regions needs to be minimized. For example, in Solomon et al., silicon raised source-drain spacers are formed so that the overlap area is reduced to that of the spacer footprint.
Sub-lithographic source and drain regions are, however, difficult to contact by subsequent metallization. By ‘sub-lithographic’, it is meant a dimension that is smaller than the minimum feature size that can be defined by conventional lithography.
In view of the foregoing, there is a need for providing a double-gate MOSFET with reduced source/drain to back-gate overlap capacitance. The present invention provides a method that is capable of reducing the overlap capacitance by making the size of source and drain regions to be as small as the footprint of a spacer. Additionally, the present invention provides a technique to form a metal-semiconductor alloy (such as, for example, silicide or germanide) and metallization to these sub-lithographic regions.